The present invention relates to a semiconductor structure applicable to semiconductor devices, such as MOSFET""s (metal oxide semiconductor field effect transistors), IGFET""s (insulated gate field effect transistors), IGBT""s (insulated gate bipolar transistors), bipolar transistors and diodes. More specifically, the present invention relates to a semiconductor structure, that provides a current path in the ON-state of the device and is depleted in the OFF-state of the device to realize a high breakdown voltage and a high current capacity.
The semiconductor devices may be classified into a lateral device, that arranges the main electrodes thereof on one major surface and makes a drift current flow parallel to the major surface, and a vertical device, that distributes the main electrodes thereof on two major surfaces facing opposite to each other and makes a drift current flow perpendicular to the major surfaces.
In the vertical semiconductor device, a drift current flows in the thickness direction of the semiconductor chip (vertically) in the ON-state of the semiconductor device and depletion layers expand also in the thickness direction of the semiconductor chip (vertically) in the OFF-state of the semiconductor device. In the conventional vertical planar-type n-channel MOSFET, the very resistive n-type drift layer thereof provides a drift current path in the ON-state of the MOSFET and is depleted in the OFF-state thereof, resulting in a high breakdown voltage.
Thinning the n-type drift layer, that is shortening the drift current path, facilitates substantially reducing the on-resistance, since the drift resistance against the drift current is reduced. However, the thinning the n-type drift layer narrows the width between the drain and the base, for that depletion layers expand from the pn-junctions between p-type base regions and the n-type drift layer. Due to the narrow expansion width of the depletion layers, the depletion electric field strength soon reaches the critical value for silicon. Therefore, breakdown is caused at a voltage lower than the designed breakdown voltage of the device. A high breakdown voltage is obtained by thickening the n-type drift layer. However, the thick n-type drift layer inevitably causes high on-resistance, that further causes loss increase. In other words, there exists a tradeoff relation between the on-resistance and the breakdown voltage.
The tradeoff relation between the on-resistance and the breakdown voltage exists in the other semiconductor devices such as IGBT""s, bipolar transistors and diodes. The tradeoff relation exists also in the lateral semiconductor devices, in that the flow direction of the drift current in the ON-state of the device and the expansion direction of the depletion layers expanded by applying a reverse bias voltage in the OFF-state of the device are different from each other.
European Patent 0 053 854, U.S. Pat. No. 5,216,275, U.S. Pat. No. 5,438,215, and Japanese Unexamined Laid Open Patent Application H09-266311 disclose semiconductor devices, which facilitate reducing the tradeoff relation between the on-resistance and the breakdown voltage. The drift layers of the disclosed semiconductor devices are formed of an alternating conductivity type layer including heavily doped n-type regions and heavily doped p-type regions arranged alternately. The alternating conductivity type layer, depleted in the OFF-state, facilitates sustaining a high breakdown voltage.
The drift layers of the disclosed semiconductor devices are not a uniform impurity diffusion layer of one conductivity type but an alternating conductivity type layer formed of n-type drift regions and p-type partition regions arranged alternately. The n-type drift regions and p-type partition regions are extended vertically.
Since the entire drift layer is depleted by the depletion layers expanding laterally from the vertically extending pn-junctions between n-type drift regions and p-type partition regions in the OFF-state of the MOSFET, a high breakdown voltage is obtained even when the impurity concentrations in the n-type drift regions and the p-type partition regions are high.
Japanese Unexamined Laid Open Patent Application No. 2000-40822 discloses the method of manufacturing such a semiconductor device including an alternating conductivity type layer. Hereinafter, the semiconductor device including an alternating conductivity type layer, that provides a current path in the ON-state of the device and is depleted in the OFF-state of the device, will be referred to as the xe2x80x9csuper-junction semiconductor devicexe2x80x9d.
Generally, the on-resistance Ron x A) of the planar-type super-junction MOSFET is described by the following formula (1).
Ronxc3x97A=(Rs+Rch+Racc+RJFET+Rdrift+Rd)xc3x97Axe2x80x83xe2x80x83(1)
Here, Rs is the resistance of the source layer, Rch the channel resistance, Racc the resistance of the accumulation layer, RJFET the resistance due to the junction FET (JFET) effect, Rdrift the drift resistance and Rd the resistance of the drain layer.
Since the drift resistance Rdrift is described by the following formula (2) for the super-junction semiconductor device, the drift resistance Rdrift increases only in proportion to the increasing breakdown voltage. Therefore, the super-junction MOSFET facilitates reducing the on-resistance much more drastically than the conventional MOSFET""s. The on-resistance is further reduced by reducing the thickness d of the n-type drift regions in the alternating conductivity type layer at the same breakdown voltage.
Rdriftxc3x97A=(4xc3x97dxc3x97Vb)/(xcexcxc3x97∈o xc3x97∈sxc3x97Ec2)xe2x80x83xe2x80x83(2)
Here, xcexc is the electron mobility, ∈o the dielectric permeability of the vacuum, ∈s the relative dielectric permeability of silicon, d the thickness of the n-type drift region, Ec the critical electric field strength, and Vb the breakdown voltage.
As the drift resistance Rdrift is reduced drastically, the other resistance components in the foregoing formula (1) become more influential. Especially, the resistance RJFET due to the JFET effect occupies a considerable part of the on-resistance. To obviate this problem, a trench-type MOSFET is proposed. The trench-type MOSFET includes trenches dug from the surface of the semiconductor chip and gate electrodes buried in the respective trenches so that channel may be created in the side wall portions of the trenches.
Although the on-resistance is reduced by aligning the trenches at a repeating pitch, where a pair of an n-type drift region and a p-type partition region is arranged repeatedly, the gate input capacitance and the feedback capacitance are increased, resulting in a low switching speed. The input capacitance increase causes an increase of the driving electric power.
In view of the foregoing, it is an object of the invention to provide a super-junction semiconductor device, that facilitates greatly reducing the tradeoff relation between the breakdown voltage and the on-resistance, preventing the input capacitance and the feedback capacitance from increasing, increasing the switching speed and further reducing the on-resistance.
According to an embodiment of the invention, there is provided a semiconductor device including: a semiconductor chip having a first major surface and a second major surface facing opposite to the first major surface; a first main electrode on the first major surface; a second main electrode on the second major surface; a layer with low electrical resistance on the side of the second major surface; an alternating conductivity type layer between the first major surface and the layer with low electrical resistance; the alternating conductivity type layer including first semiconductor regions of a first conductivity type and second semiconductor regions of a second conductivity type arranged alternately; a pair of the first semiconductor region and the second semiconductor region being repeated at a first repeating pitch; trenches dug from the first major surface; a gate electrode buried in each of the trenches with a gate oxide film interposed therebetween; the gate electrodes being arranged repeatedly at a second repeating pitch different from the first repeating pitch; well regions of the second conductivity type in contact with the gate oxide films in the side walls of the trenches; and source regions of the first conductivity type isolated by the well regions from the first semiconductor regions, the source regions contacting with the gate oxide films in the side walls of the trenches.
Preferably, the second repeating pitch is wider than the first repeating pitch.
Since the gate area per unit area is reduced by setting the second repeating pitch, where the gate electrodes or the trenches are arranged repeatedly, more widely than the first repeating pitch, where a pair of the first semiconductor regions and the second semiconductor regions is arranged repeatedly, the input capacitance and the feedback capacitance are reduced.
Preferably, the semiconductor device further includes one or more third semiconductor regions of the first conductivity type between the well regions and the alternate arrangement of the first semiconductor regions and the second semiconductor regions, the one or more third semiconductor regions being connected to the first semiconductor regions.
Since the first semiconductor regions are connected to each other through the one or more third semiconductor regions, the input capacitance and the feedback capacitance are reduced without increasing the on-resistance as much.
According to another embodiment of the invention, there is provided a planar-type semiconductor device including: a semiconductor chip having a first major surface and a second major surface facing opposite to the first major surface; a first main electrode on the first major surface; a second main electrode on the second major surface; a layer with low electrical resistance on the side of the second major surface; an alternating conductivity type layer between the first major surface and the layer with low electrical resistance; the alternating conductivity type layer including first semiconductor regions of a first conductivity type and second semiconductor regions of a second conductivity type arranged alternately; a pair of the first semiconductor region and the second semiconductor region being repeated at a first repeating pitch; gate electrodes above the first major surface of the semiconductor chip with gate oxide films interposed therebetween; the gate electrodes being arranged repeatedly at a second repeating pitch different from the first repeating pitch; well regions of the second conductivity type in contact with the gate oxide films; source regions of the first conductivity type isolated by the well regions from the first semiconductor regions, the source regions contacting with the gate oxide films; and one or more third semiconductor regions of the first conductivity type between the well regions and the alternate arrangement of the first semiconductor regions and the second semiconductor regions, the one or more third semiconductor regions being connected to the first semiconductor regions.
Preferably, the trenches are dug deeply enough to reach the one or more third semiconductor regions. Preferably, the trenches are dug deeply enough to reach the inside portions of the first semiconductor regions.
When the trenches are deep enough to reach the one or more third semiconductor regions, it is not necessary to adjust the locations of the trenches and the locations of the first semiconductor regions and the on-resistance is reduced to some extents.
Preferably, the horizontal arrangement of the gate electrodes or the trenches is shaped with a stripe pattern.
Although the horizontal arrangement of the gate electrodes or the trenches may be shaped with a stripe pattern or a cell pattern, the stripe pattern is preferable for easy manufacture.
Preferably, the net impurity concentrations in the first semiconductor regions and the second semiconductor regions are almost the same.
When the net impurity concentrations in the first semiconductor regions and the second semiconductor regions are almost the same, a high breakdown voltage is obtained independently of the shapes of the first semiconductor regions and the second semiconductor regions.
Preferably, the boundaries between the first semiconductor regions and the second semiconductor regions extend almost perpendicular to the first major surface or the second major surface of the semiconductor chip.
When the boundaries between the first semiconductor regions and the second semiconductor regions extend obliquely to the first major surface, it is difficult to obtain a high breakdown voltage, since the portions, thereto the electric field localizes, are caused, and the on-resistance increases, since the substantial drift length is prolonged.
Preferably, the first semiconductor regions and the second semiconductor regions are shaped with respective stripes.
When the first semiconductor regions and the second semiconductor regions are shaped with respective stripes, the first semiconductor regions and the second semiconductor regions are patterned easily and the net impurity concentrations in the first semiconductor regions and the second semiconductor regions are adjusted easily.
Preferably, the stripes of the first semiconductor regions and the second semiconductor regions extend almost perpendicular to the stripes of the gate electrodes.
When the stripes of the first semiconductor regions and the second semiconductor regions are extended perpendicular to the stripes of the gate electrodes, it is not necessary to precisely adjust the locations of the gate electrodes or the trenches and easy manufacture of the semiconductor device is facilitated.
Preferably, the first semiconductor regions or the second semiconductor regions are located at the lattice points of a two-dimensional trigonal lattice, a two-dimensional orthogonal lattice or a two-dimensional hexagonal lattice.
When the net impurity amounts in the first semiconductor regions and the second semiconductor regions are the same, a high breakdown voltage is obtained independently of the shapes of the first semiconductor regions and the second semiconductor regions.
Preferably, the trenches with the gate electrodes buried therein are arranged like a two-dimensional trigonal lattice, a two-dimensional orthogonal lattice or a two-dimensional hexagonal lattice. The trenches may be shaped with various shapes.